- Readout takes 95 s for a 2048 × 2304 pixel subarray. That's 4.6 megapixels in 95 s or 50 kHz.
- Clearly, each ADC must do 5 × 104 conversions per second to keep up with the optimum conversion rate.
- Since the read noise is 3 electrons, reading single electrons/read is not justifiable. If we set the gain so that 1 LSB = 2 electrons (so we can still see the read noise), and full well is 100,000 electrons, that's a dynamic range of 50,000, which requires a 16 bit converter.
- Looking up 16 bit, 50 kHz ADCs, there are many successive approximation converters that work even faster than this. However, using SA means we'll need a sample and hold to record the signal from each pixel. What about Σ-Δ? In high speed mode, the ADS 1278-ht, for example, takes over 50 kilosamples/s. At that speed, its signal to noise ratio is 106 dB with 8.5 µV RMS noise. Given that full scale is specified as 0.45 V, we require noise in the ADC of no more than 1/5×104 of that or 9 µV -- just what this ADC delivers. Thus, while the nominal specification for the ADS 1278-ht is for a 24 bit device, we can use it as a 16 bit converter. Considering that the output of each pixel's sampling will require settling time due to RC time constants, it is probably best to use a sample and hold and a successive approximations converter, but sample and hold plus Σ-Δ might also work.
- At full well, N = (100,000 + 32)1/2 = 316 counts for S/N = 316 at best. At low signal levels, say, 10 detected electrons, N = (10 + 32)1/2 = 4.35, or S/N = 10/4.35 = 2.5.
- Given the lower read noise here, the CCD is better for low-intensity signals. It is also better for wide dynamic range signals (useful from 10 photons to 100,000 photons detected, vs. 25 to 60,000 for CMOS). CMOS is better for rapidly changing signals since readout time is shorter.