# DAC Coding Schemes

Please review Number Representation before proceeding if you aren't comfortable with the various binary and hexadecimal ways of representing numbers.

For straight binary, unipolar coding, the R/2R network described in Ladder Networks is all that is needed. What about other representations of binary numbers?

For offset binary, an offset potential can be summed with the potential coming out of the R/2R ladder. Suppose the reference potential is -V_{0}, so that the output for an N-bit coding would be from -V_{0} (binary code 0) to 0 (binary code 2^{N-1}) to (2^{N-1}-1)/(2^{N-1})V_{0}. From input codes of 0 to 2^{N-1}-1,
output should follow exactly the pattern already given for straight binary, but offset by V_{0}. From
2^{N-1} to
2^{N}-1,
the output is the same as for a straight binary network, ignoring the most significant bit. Another way to say that is that offset binary for N bits goes through straight binary encoding for N-1 bits twice, once with a -V_{0}
offset, and once without. You can show (or, at least, it can be shown) that the output of the following circuit is V_{1} - V_{2}:

If the output of the straight binary ladder network goes into V_{2}, then
we need only apply -V_{0} to
V_{1} for inputs of binary 0 to
2^{N-1}-1, and apply 0 to
V_{1} for the other codes. It's just one more switch, and that switch can be directly controlled in the same way as the switches in the ladder network.

For 2's complement binary,
codes from 0 to
2^{N-1}-1
act just the same as they do for straight binary. But what about from 2^{N-1} to 2^{N}-1? The output needs to be negative AND the coding isn't as direct as for the previous two codings. How did we handle binary subtraction when we talked about two's complement binary? By complementing, incrementing, and adding. Hey, we can play that game again! If the most significant bit is set,

a) set the ladder switches based on complemented and incremented remaining bits.

b) switch the output of the ladder from the inverting input of the summing amplifer to the non-inverting input.

That's it! And because this technology has been around for many years, it's all done in a nice, compact package. **The point is that the coding of the DAC and the coding sent to the DAC from the computer have to match.**

Finally, there is an almost magical device, a multiplying digital to analog converter or MDAC.
The reference potential, instead of being a fixed value, can come from anywhere -- an analog signal, or another DAC. So let's suppose we want to multiply a potential times some scale factor that changes over time. Perhaps we have incoming data that ranges from 10 mV to 10 V, but we always want an output in the range from 10 mV to 100 mV. That means we need to scale the voltage by 1 (for inputs between 10 and 100 millivolts), by 0.10 (inputs between 0.1 and 1 V), or by 0.01 (inputs from 1 V to 10 V). What to do? Use the analog signal, scaled by 2^{N}/2^{N}-1 as the reference input to an MDAC! If we then use straight binary coding to the MDAC, when we put in a full scale code of 2^{N}-1, the output = V_{observed}. But if we put in a code of (2^{N}-1)/10, we scale the output down by a factor of 10, and if we put in a code of
(2^{N}-1)/100, we scale down by a factor of 100. So now we can use a computer to control the magnitude of an analog signal. "But wait a second," you protest (or at least one hopes you protest). "Suppose I have an 8 bit converter. 2^{8} = 256.
If I run at full scale,

V_{out} = (2^{8}/(2^{8}-1))*(2^{8}-1) * V_{observed} = V_{observed}.

But if I want
2^{8}/10, I can't do it exactly; 255/10 = 25.5, and I can't represent that exactly as a digital number! Oops.

There are several ways around this problem.

a) Use binary-coded decimal MDACs. Instead of ladder networks designed for base 2, they use ladder networks designed for base 10. Brute force, but it works.

b) Use more binary bits than the minimum, and use a number that is sufficiently close to the scale factor desired that the error is insignificant.

For example, let's suppose we're using a 12 bit converter (quite common). Then for full scale,

V_{out} = (2^{12}/(2^{12}-1))*(2^{12}-1) * V_{observed} = V_{observed}.

But 2^{12}=4096, so 2^{12}/10 = 409.6 which rounds off to 410, and error of only 0.4/410 = 0.1%. 2^{12}/100 = 40.96 which rounds to 41, an error, similarly, of 0.1%. Good enough for most purposes.

As digital signal processors (DSPs) have become more sophisticated and faster, the need for MDACs has declined. Data is digitized, the DSP scales the digital representation into the desired range, and then uses an ordinary DAC to generate a fresh analog signal. Nevertheless, if one needs a very high speed analog multiplier, there are times that an MDAC is the cheapest, easiest way to do it.