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Sample and Hold Settling Time

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Ignoring all nonidealities, recall that it takes longer than one RC time constant to accurately reach a steady state voltage on a capacitor. Let's do another exercise. Recall that Vcap = Vstep(1-exp-t/RC). So let's figure out how long it takes to get the accuracy of a sample and hold circuit to some number of bits. We already worked problems like this in the section on digital to analog conversion.

If RC = 1 μs, how long must the sampling switch for the sample and hold stay closed to get the capacitor charged adequately for 16 bit accuracy?




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