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Sigma-Delta ADC

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A Σ-Δ converter runs perpetually, seeking to produce an analog output that matches the input potential. It does this by integrating the difference between the output of a 1 bit DAC and the value of the input signal. The DAC outputs either +Vref or -Vref. If the input potential is 0, then, on average, half the time the DAC will need be set to logical 1 (+Vref), and half the time to logical 0 (-Vref). A comparator looks at the difference between the integrated voltage on the capacitor and the instantaneous input. While positive noise bursts may lead to a burst of counted pulses, negative noise bursts will lead to a period during which pulses are absent. By continously chasing perfection, the counts from noise average out. One counts the number of logical 1's over a fixed period, knowing that all 1's implies an input of +Vref or greater, all 0's implies -Vref or less, and all counts in between imply intermediate values. The comparator/integrator/1 bit value setting has to occur many times for each digitization. In fact, typically, one oversamples, that is, measures the signal more than the minimum plausible number of times before outputting a single value. Suppose one seeks an output precise to 24 bits. That's about 1 part in 16 million. At an oversampling of 16, that means 16*16 milliion = 256 million comparisons must have been made. For a single integrator/single bit DAC, that would allow 1 conversion per second with this oversampling and a comparison made every 4 ns. In practice, one doesn't simply count pulses flat-footedly, but rather digitally filters the bitstream. The result is that a nominal 24 bit ADC can be speeded up to be a multi-kilohertz, lower resolution device, or slowed down to be a full 24 bit, few-Hertz-converter.

   
 

 

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