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Successive Approximations ADC

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The key here is that we synthesize a voltage using a DAC, compare the DAC's output voltage to the signal input voltage, then increase or decrease the DAC's output until the code feeding the DAC gives the closest possible match to the potential of the input signal. For the simplest possible example, let's use a 1 bit DAC. The full scale signal will be +5 V, and 0 will correspond to 0. Thus, if the input is over +2.5 V, the output should be with the DAC's bit set. Otherwise, the DAC output should be 0. How do we proceed?

1) Trigger the sample and hold to hold the input value.

2) Guess that the digitized value is 1. Feed that logical 1 to a 1 bit DAC which puts out 1/2 of the ADC's full range, or +2.5 V.

3) Use a comparator to look at the DAC output and the held signal from the sample and hold. If the sampled value is ≥ 2.5 V, the comparator output will be high. If the sampled value is < 2.5 V, the comparator output will be low.

4) If the comparator output is high, the digitized value is 1; otherwise, the single bit is too big to represent the input signal, so we set it back to 0 and we're done.

A picture may help:

S&H+ADC

Note that if the DAC output is greater than the sample and hold output, the comparator output is high, while if the DAC output is lower than the sampled value, the comparator output is low.

   
 

 

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