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Successive Approximations ADC

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Hybrid Converters

Suppose there's a signal that is always between 2.8 and 3.2 volts. The first 4 bits of the digitized word will always be 1001. Doesn't it seem wasteful (4 comparator operations!) to start fresh every time to convert these bits when it is only the less significant bits that are changing? We could probably speed up the conversion if we didn't waste time on digitizing the slowly-varying, large amplitude part of the potential. Engineers, being clever, have reached the same conclusion and have designed hybrid ADCs that use flash converters for the most significant bits, then successive approximations (or sigma-delta) for less significant bits. The first 8 bits are digitized in a single cycle and feed the 8 most significant bits of the DAC. As long as the output precision of the DAC is good enough, one can then do an analog subtraction of the DAC output from the original (sampled) signal to provide the input for the successive approximations part of the circuit. Here's a sketch:





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