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Successive Approximations ADC

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Why digitize the 8 most-significant bits and then reconvert them to analog before subtracting? Recall that the comparators in the flash ADC are subject to error and thus they only approximately carry out digitization. If the output of the 8 bit DAC is PRECISE to 12-18 bits, then a precision offset can be introduced before the least-significant bits are digitized. The subtraction amplifer (the bottom operational amplifier in the figure) can be designed with gain so that differences of a few millivolts between the sampled voltage and the DAC output are presented to the second ADC at 2×, 10×, or 100× the actual difference, so the second ADC can use higher, less noise-susceptible potentials. Are there additional "gotcha"s? Yes -- and we'll discuss those under Bits, Noise, and Linearity.




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