# Voltage to Frequency Conversion ADC

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If we count pulses for a fixed period of time, then we know how often the comparator tripped during that time. Suppose we want to display 1.000 for a 1 V input, and suppose we look at the input for 1.000 s. Then we'd want the comparator to trip 1000 times per second. Further, suppose the comparator is set up to trip at a potential of 5 V (chosen just so it's not the same as the input potential; in fact, this potential can be anything we like as long as we know it in advance). Then a 1 V input should integrate to 5 V in 1 ms. In the dual slope module, we explained how integrators work. From the argument there, the RC time constant of the integrator is set by Vout = - VinT/(RC). Ignoring sign, 5 V = 1 V * 1 ms/RC.
RC = 1 ms/5 = 200 μs. For R = 1 kΩ, C = 0.2 μF. Changing the expected magnitude of the input voltage or the number of significant figures desired may mean a different integration time, R, or C value, but for a wide range of inputs the integrate, short, count, repeat cycle works well. The first very high resolution (up to 6 digits or ~ 20 bits) ADCs worked on this principle.

The non-idealities of a V to F converter are dependent on the design strategy. Let's start the simplest approach. Here, we do nothing to compensate for the time required to fully discharge the capacitor; the time while the capacitor is discharging called "dead time." The bigger the resistance of the switch used to short the capacitor, the longer the switch must be closed. Alternatively, if the switch isn't closed for long enough, there will be residual potential on the integrator, and the time to integrate to threshold will be reduced. In practice, if one knows how long the switch is closed, one knows how long the dead time is, and a correction factor may be computed.